GENERAL DESCRIPTION
The 1 Mbit Embedded DRAM (EmDRAM) is an asynchronous design with non-multiplexed row and column  addressing scheme. The memory operations are controlled by RAS, CASH/CASL, and WE. Byte access is  controlled by CASH (upper byte) and CASL (lower byte).
The EmDRAM has been designed to support 200Mbyte  data rate with a 30 ns latency when operated in the page  mode with extended data output (EDO). this maximum  rate can be sustained for one page of 12 bytes.

FEATURES
◆ Logical organization: 64k x 16 bits
◆ Physical organization: 256 x 256 x 16
◆ Single 3.3V ±0.3V power supply
◆ 256 cycle refresh in 4 ms
◆ Refresh modes: RAS only, CBR, and Hidden
◆ Dual CAS for Byte Write and Byte Read control
◆ Separate I/O operation
◆ 100 MHz page mode EDO cycle
◆ 30 ns row access time
◆ Redundancy: 2 WL/256K, 2 CS/1M