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F59L4G81XB-25BCG2X 데이터시트 - [Elite Semiconductor Memory Technology Inc.

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F59L4G81XB-25BCG2X

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ESMT
[Elite Semiconductor Memory Technology Inc. ESMT

GENERAL DESCRIPTION
NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.


FEATURES
● Operating voltage range
   ― VCC: 2.7–3.6V
● Open NAND Flash Interface (ONFI) 1.0-compliant1
● Single-level cell (SLC) technology
● Organization
   ― Page size: 4352 bytes (4096 + 256 bytes)
   ― Block size: 64 pages
   ― Number of planes: 1
● Asynchronous I/O performance
   ― tRC/tWC: 25ns
● Array performance
   ― Read page: 115μs (MAX) with on-die ECC enabled
   ― Read page: 25μs (MAX) with on-die ECC disabled
   ― Program page: 200μs (TYP) with on-die ECC
      disabled
   ― Program page: 240μs (TYP) with on-die ECC enabled
   ― Erase block: 2ms (TYP)
● Command set: ONFI NAND Flash protocol
● Advanced command set
   ― Program page cache mode
   ― Read page cache mode
   ― Permanent block locking (blocks 47:0)
   ― One-time programmable (OTP) mode
   ― Block lock
   ― Programmable drive strength
● Operation status byte provides software method for
   detecting
   ― Operation completion
   ― Pass/Fail condition
   ― Write-protect status
● Ready/Busy# (R/B#) signal provides a hardware method
   of detecting operation completion
● WP# signal: Write protect entire device
● ECC: 8-bit internal ECC is disabled at default2. It can be
   toggled using the SET FEATURE command
● Blocks 0 is valid when shipped from factory with ECC. For
   minimum required ECC, see Error Management.
● RESET (FFh) required as first command after power- on.
● Internal data move operations supported within the plane
   from which data is read
● Quality and reliability
   ― Endurance: 100,000 PROGRAM/ERASE cycles
   ― Data retention: JESD47G-compliant; see qualification
      report
   ― Additional: Uncycled data retention: 10 years 24/7 @
      70°C
   ― Read unique ID
   ― Internal data move


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