[ChipON]

Overview
The chip for the Harvard structure of the streamlined instruction CPU. In this structure, the program and the data access bus are independent of each other of. The instruction byte length is 16 bits, all instructions are single-byte instructions, and most instructions can be executed in a machine cycle Line finished. A total of 49 instructions, high efficiency, easy to expand the instruction. The chip integrates a variety of peripherals, including one 8-bit timer / counter, a 16-bit timer / counter, 2-way 8-bit PWM module, an analog comparator / Test voltage module, analog-to-digital conversion ADC module, hardware watchdog and low voltage detection and low voltage reset module. The chip integrates 64X8 bit asynchronous low power SRAM and 1KX16 bit program memory.
Chip characteristics
● CPU
   A high-performance RISC CPU
   Only 49 instructions
   Supports interrupt handling
● Instruction
   The operating frequency is DC ~ 20MHZ, one machine cycle is 4 clock cycles In addition to the part of the jump instruction requires two machine cycles, the other instructions are a machine cycle
● memory
   Support direct, indirect and relative addressing in three ways 1KX16 bit FLASH program memory 64 bytes of data memory
   The reset vector is at 0000H and the interrupt vector is at 0004H Level 8 hardware stack structure
● Special features
   Built-in power-on reset circuit
   Low voltage detection and low voltage reset
   Hardware watchdog
   Supports online serial programming (ICSP)
   Low power sleep mode
   Internal software Optional clock frequency 62.5KHZ ~ 16MHZ
● Timer / Counter
   Timer 0: 8-bit timer / counter with 8-bit prescaler
   Timer 1: 16-bit timer / counter with gating and prescaler
● Other peripherals
   2-channel 8-bit pulse width modulation PWM module
   - (operational amplifier) ​​analog comparator
   - reference voltage module
   - 12-bit 8/7 channel ADC module
● working conditions
   Working voltage: 2.5V ~ 5.5V
   Operating temperature range: -40 ~ 85 ℃