Description
This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high-efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(on) per footprint area.

FEATUREs
• LD-MOS Technology with the Lowest Figure of Merit:
   -RDS(on) = 8.2mΩ to Minimize On-State Losses
   -Qg = 8.1nC for Ultra-Fast Switching
• Vgs(th) = -0.8V typ. for a Low Turn-On Potential
• CSP with Footprint 1.5mm × 1.5mm
• Height = 0.60mm for Low Profile
• ESD = 6kV HBM Protection of Gate
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. “Green” Device (Note 3)
• Qualified to AEC-Q101 Standards for High Reliability

APPLICATIONs
• DC-DC Converters
• Battery Management
• Load Switch