CP704 데이터시트 - Central Semiconductor
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CP704
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Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 22 x 22 MILS
Die Thickness 9.0 MILS
Base Bonding Pad Area 3.7 X 3.7 MILS
Emitter Bonding Pad Area 4.2 X 4.2 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au - 18,000Å
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Small Signal Transistor PNP - High Current Transistor Chip ( Rev : 2010 )
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