Description
The ATA6622 is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for 3.3V/50 mA output and a window watchdog. The ATA6624 has the same functionality as the ATA6622; however, it uses a 5V/50 mA regulator. The ATA6626 has the same functionality as ATA6624 without a TXD time-out timer. The voltage regulator is able to source 50 mA, but the output current can be boosted by using an external NPN transistor. This chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for LIN-bus systems.

FEATUREs
• Master and Slave Operation Possible
• Supply Voltage up to 40V
• Operating voltage VS = 5V to 27V
• Typically 10 µA Supply Current During Sleep Mode
• Typically 57 µA Supply Current in Silent Mode
• Linear Low-drop Voltage Regulator:
   – Normal, Fail-safe, and Silent Mode
   – ATA6622 VCC = 3.3V ±2%
   – ATA6624 VCC = 5.0V ±2%
   – ATA6626 VCC = 5.0V ±2%, TXD Time-out Timer Disabled
   – In Sleep Mode VCC is Switched Off
• VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical Combined at Open Drain Output NRES
• Negative Trigger Input for Watchdog
• Boosting the Voltage Regulator Possible with an External NPN Transistor
• LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2
• Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin
• INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up Resistor
• TXD Time-out Timer; ATA6626: TXD Time-out Timer Is Disabled
• Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery
• Adjustable Watchdog Time via External Resistor
• Advanced EMC and ESD Performance
• ESD HBM 8 kV at Pins LIN and VS According to STM5.1
• Package: QFN 5 mm × 5 mm with 20 Pins