Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power consumption in CMOS standby mode.

Features
• AS7C4096 (5V version)
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA