Functional description
The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

FEATUREs
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
   - 10/12/15/20 ns address access time
   - 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
   - 288 mW / max @ 10 ns
• Low power consumption: STANDBY
   - 18 mW / max CMOS I/O
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
   - 44-pin 400 mil SOJ
   - 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA