DESCRIPTION
   The 4.2Gb DDR2 SDRAM, a high-speed CMOS, dynamic random-access memory containing 4,294,967,296 bits. Each of the four chips in the MCP are internally configured as 8-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3.

FEATURES
◾ DDR2 Data rate = 667, 533, 400
◾ Available in Industrial, Enhanced and Extended Temp
◾ Package:
   • Proprietary Enchanced Die Stacked iPEM
   • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm
   • 1.00mm ball pitch
◾ Differential data strobe (DQS, DQS#) per byte
◾ Internal, pipelined, double data rate architecture
◾ 4n-bit prefetch architecture
◾ DLL for alignment of DQ and DQS transitions with
   clock signal
◾ Eightinternal banks for concurrent operation
   (Per DDR2 SDRAM Die)
◾ Programmable Burst lengths: 4 or 8
◾ Auto Refresh and Self Refresh Modes (I/T Version)
◾ On Die Termination (ODT)
◾ Adjustable data – output drive strength
◾ 1.8V ±0.1V common core power and I/O supply
◾ Programmable CAS latency: 3, 4, 5, 6 or 7
◾ Posted CAS additive latency: 0, 1, 2, 3, 4 or 5
◾ Write latency = Read latency - 1* tCK
◾ Organized as 64M x 64
◾ Weight: AS4DDR264M64PBG1 ~ 2.0 grams typical

BenefitS
◾ 58% Space Savings
◾ 49% I/O reduction vs Individual CSP approach
◾ Reduced part count
◾ Reduced trace lengths for lower parasitic
   capacitance
◾ Suitable for hi-reliability applications
◾ Upgradable to 128M x 64 density in future
◾ Pin / Function equivalent to White
   W3H64M64E-xSBx