FEATURES
   Excellent intrinsic jitter performance
   25 Mb/s write-speed serial I/O control
   200 MHz phase frequency detector inputs
   655 MHz programmable input dividers for the phase
      frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
   Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
   8 programmable internal clock rates
   Programmable edge delay with 93 fS resolution
   1.8 V supply for device operation
   3.3 V supply for I/O, CML driver, and charge pump output
   Software controlled power-down
   48-lead LFCSP package
   Programmable charge pump current (up to 4 mA)
   Multichip synchronization
   Dual-mode PLL lock detect
   655 MHz CML-mode PECL-compliant driver

APPLICATIONS
   Clocking high performance data converters
   Base station clocking applications
   Network (SONET/SDH) clocking
   Gigabit Ethernet (GbE) clocking
   Instrumentation clocking circuits