[Zentel]

General Description
A3V56S30ETP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and A3V56S40ETP is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. A3V56S30ETP and A3V56S40ETP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.

FEATUREs
- Single 3.3V ±0.3V power supply
- Maximum clock frequency :
- 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQM (A3V56S30ETP), DQML and DQMU (A3V56S40ETP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Support concurrent auto-precharge
- Auto and self refresh
- 8192 refresh cycles /64ms
- LVTTL Interface
- Package
    400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch Pb-free package is available