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74LVX112MTC 데이터시트 - Fairchild Semiconductor

74LVX112 image

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74LVX112MTC

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Fairchild
Fairchild Semiconductor Fairchild

General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs (J, K, PRESET, CLEAR, and CLOCK) and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock.
The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.


FEATUREs
■ Input voltage level translation from 5V–3V
■ Ideal for low power/low noise 3.3V applications

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제조사
Dual J-K Flip-Flops with Preset and Clear
Fairchild Semiconductor
Dual J-K Flip-Flops (with Preset and Clear)
Hitachi -> Renesas Electronics
Dual J-K Flip-Flops with Clear and Preset
Fairchild Semiconductor
Dual J-K Flip-Flops (with Preset and Clear)
Hitachi -> Renesas Electronics
Dual J-K Flip-Flops (with Preset and Clear)
Renesas Electronics
DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR
ON Semiconductor
Dual J-K Flip-Flops with Preset and Clear ( Rev : 2007 )
Fairchild Semiconductor
Dual J-K Flip-Flops with Clear and Preset
Fairchild Semiconductor
Dual J-K Flip-Flops (with Preset and Clear)
Renesas Electronics
Dual J-K Flip-Flops (with Preset)
Renesas Electronics

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