General description
The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.
The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices in a mixed 3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

FEATUREs
■ Wide supply voltage range from 1.65 to 5.5 V
■ High noise immunity
■ Complies with JEDEC standard:
    ◆ JESD8-7 (1.65 V to 1.95 V)
    ◆ JESD8-5 (2.3 V to 2.7 V)
    ◆ JESD8B/JESD36 (2.7 V to 3.6 V)
■ ±24 mA output drive (VCC = 3.0 V)
■ Latch-up performance exceeds 250 mA
■ CMOS low power consumption
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ ESD protection:
    ◆ HBM EIA/JESD22-A114E exceeds 2000 V
    ◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ SOT363 and SOT457 package
■ Specified from −40 to +85 °C and −40 to +125 °C.