3-STATE HEX BUFFERS

Thesedevices are high speed hex buffers with 3-state outputs. They are organizedas single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D) paths.The outputs are designed to drive 15TTL Unit Loads or 60 Low Power Schottky loads when the Enable (E) is LOW.
Whenthe Output Enable (E) is HIGH, the outputsare forced to a high impedance “off” state. If the outputs of the 3-state devices are tied together, allbut one device must be in the high impedance state to avoid high currents
thatwould exceed the maximum ratings. Designers should ensure that Output Enablesignals to 3-state devices whose outputs are tied togetherare designed so there is no overlap.