DESCRIPTION
The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individualJ,K,clock,andasynchronous setandclearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs areequipped withprotectioncircuitsagainst static discharge and transient excess voltage.

. HIGH SPEED
   fMAX = 67 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
   ICC = 2 µA AT TA = 25 °C
. HIGH NOISE IMMUNITY
   VNIH = VNIL= 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
   |IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
   tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
   VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH 54/74LS112