BR24Gxxx-3A (128K 256K 1M)
Software Reset
Software reset is executed to avoid malfunction after power ON, and during command input. Software reset has several
kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 45-(a), Figure 45-(b), Figure 45-(c)) Within the
dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may be
output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
SCL
SDA
Dummy clock×14
Start×2
12
13 14
Normal command
Normal command
SCL
SDA
Figure 45-(a). The Case of Dummy Clock × 14 +START+START+ Command Input
Start
Dummy clock×9
Start
12
89
Normal command
Normal command
Figure 45-(b). The Case of START + Dummy Clock × 9 +START+ Command Input
SCL
SDA
Acknowledge Polling
Start×9
1 23
7 89
Normal command
Normal command
Figure 45-(c). START×9+ Command Input
※Start command from START input.
During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge
polling, next command can be executed without waiting for tWR = 5ms.
To write continuously, R/W = 0, then to carry out current read cycle after write, slave address with R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
First write command
During internal write,
ACK = HIGH is returned.
S
S
T
T
A Write command O
R
P
T
S
T Slave
A
R address
A
C
K
H
S
T Slave
A
R address
A
C
K
H
…
T
T
tWR
Second write command
…
S
T Slave
A
R
address
A
C
K
H
T
tWR
S
T Slave
A
R address
A
C
K
L
Word
address
A
C
K
L
Data
T
AS
CT
KO
LP
After completion of internal write,
ACK=LOW is returned, so input next
word address and data in succession.
Figure 46. Case to Continuous Write by Acknowledge Polling
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24.Mar.2020 Rev.008