BR24A64-WM(2009) 데이터 시트보기 (PDF) - ROHM Semiconductor
부품명
상세내역
일치하는 목록
BR24A64-WM Datasheet PDF : 18 Pages
| |||
BR24A□□-WM series
Technical Note
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be
read in succession.
SDA
L IN E
S
W
T
R
A
I
R
SLAVE
T
T ADDRESS E
W ORD
ADDRESS(n)
S
T
R
A
E
R
SLAVE
A
T ADDRESS D
S
T
O
DATA(n)
P
1 0 1 0 A 2A 1A 0
WA
7
N o te )
R A *1
/C
WK
WA
0
A
C
K
1 0 1 0 A 2 A 1A 0
D7
RA
/C
WK
D0
A
C
K
Fig.42 Random read cycle (BR24A01A/02/04/08/16-WM)
It is necessary to input 'H' to
the last ACK.
*1 As for WA7, BR24A01A-WM become Don’t care.
SDA
LINE
S
W
T
R
A
R
T
SLAVE
ADDRESS
I
T
E
1st WORD
ADDRESS（ｎ）
1 0 1 0 A2A1A0
* * * WAWA
12 11
S
T
R
S
2nd WORD
ADDRESS（ｎ）
A
R
T
SLAVE
ADDRESS
E
A
D
DATA(n)
T
O
P
WA
0
1 0 1 0 A2A1A0
D7
D0
Note)
RA
/C
*1
A
C
WK
K
A
RA
C
/C
K
WK
Fig.43 Random read cycle (BR24A32/64 -WM)
A
C
K
*1 As for WA12, BR24A32-WM become Don’t care.
SDA
L IN E
S
T
R
A
E
R
SLAVE
A
T ADDRESS D
S
T
O
D A T A (n )
P
1 0 1 0 A 2A 1A 0
D7
D0
RA
A
N o te )
/C
WK
C
K
Fig.44 Current read cycle
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
1 0 1 0 A2 A1A0
D7
D0
S
T
DATA(n+x)
O
P
D7
D0
It is necessary to input 'H' to
the last ACK.
RA
A
A
A
Note）
/C
WK
C
K
C
K
C
K
Fig.45 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
Fig.46 Difference of slave address of each type
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and BR24A16-WM, A0 becomes P0.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
10/17
2009.08 - Rev.C
Share Link: 