74ALVCH16600DGG 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74ALVCH16600DGG Datasheet PDF : 17 Pages
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74ALVCH16600
18-bit universal bus transceiver; 3-state
Rev. 3 — 15 January 2018
Product data sheet
1 General description
The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-state
bus compatible outputs in both send and receive directions. Data flow in each direction
is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA),
and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if
CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in
the flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is LOW, the outputs
are active. When OEAB is HIGH, the outputs are in the high-impedance state. The HIGH
clock can be controlled with the clock-enable inputs (CEBA and CEAB).
Data flow for B-to-A is similar to that of A-to-B, but uses OEBA, LEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB
should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2 Features and benefits
• CMOS low power consumption
• MultiByte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Bus hold on data inputs
• Output drive capability 50 Ω transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V
• Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
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