74ALVCH16600DGG 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74ALVCH16600DGG Datasheet PDF : 17 Pages
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Nexperia
74ALVCH16600
18-bit universal bus transceiver; 3-state
10.1 Waveforms and test circuit
VI
An, Bn
input
VM
VM
GND
VOH
Bn, An
output
VOL
tPHL
VM
tPLH
VM
001aal734
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 6. The input An, Bn to output Bn, An propagation delay times.
CPBA, CPAB
input
VI
1/fmax
LEBA,
LEAB
input
GND
VOH
VM
VM
tW
tPHL
VM
tPLH
An, Bn
output
VM
VOL
VM
aaa-028032
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 7. Latch enable input LEAB, LEBA and clock input CPAB, CPBA to output Bn, An propagation delay times;
pulse width and fmax of CPAB and CPBA
VI
OEAB, OEBA
input
VM
VM
GND
VCC
An, Bn output
LOW-to-OFF
OFF-to-LOW
VOL
VOH
An, Bn output
HIGH-to-OFF
OFF-to-HIGH
GND
tPLZ
tPZL
tPHZ
VX
VY
outputs
enabled
VM
tPZH
outputs
disabled
VM
outputs
enabled
aaa-028033
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 8. 3-state enable and disable times.
74ALVCH16600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 January 2018
© Nexperia B.V. 2018. All rights reserved.
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