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LTC4307-1
Linear Technology
LTC4307-1 Datasheet PDF : 12 Pages
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LTC4307-1
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
VTHR_ENABLE ENABLE Threshold
IENABLE
ENABLE Input Current
tPLH_EN
ENABLE Delay Off-On
tPHL_EN
ENABLE Delay On-Off
tPLH_READY READY Delay Off-On
tPHL_READY READY Delay On-Off
VOL_READY
READY Output Low Voltage
IOFF_READY
READY Off Leakage Current
Propagation Delay
ENABLE from 0V to VCC
VCC = 3.3V (Figure 1)
VCC = 3.3V (Note 3) (Figure 1)
VCC = 3.3V (Note 3) (Figure 1)
VCC = 3.3V (Note 3) (Figure 1)
IPULLUP = 3mA, VCC = 2.3V
VCC = READY = 5.5V
0.8
1.4
2
●
0.1
±5
95
10
10
10
●
0.4
●
0.1
±5
tPHL
SDA/SCL Propagation Delay High to Low
tPLH
SDA/SCL Propagation Delay Low to High
tFALL
SDA/SCL Transition Time High to Low
Input-Output Connection
CLOAD = 50pF, 2.7k to VCC on SDA, SCL,
VCC = 3.3V (Notes 2, 3) (Figure 1)
CLOAD = 50pF, 2.7k to VCC on SDA, SCL,
VCC = 3.3V (Notes 2, 3) (Figure 1)
CLOAD = 100pF, 10k to VCC on SDA, SCL,
VCC = 3.3V (Notes 3, 4) (Figure 1)
70
10
30
300
VOS
Input-Output Offset Voltage
2.7k to VCC on SDA, SCL, VCC = 3.3V,
Driven SDA, SCL = 0.2V
● 20
60
100
VTHR
SDA, SCL Logic Input Threshold Voltage Rising Edge
VHYS
SDA, SCL Logic Input Threshold Voltage (Note 3)
Hysteresis
0.45VCC 0.55VCC 0.65VCC
50
CIN
Digital Input Capacitance SDAIN, SDAOUT, (Note 3)
10
SCLIN, SCLOUT
ILEAK
Input Leakage Current
VOL
Output Low Voltage
SDA, SCL, Pins
SDA, SCL Pins, ISINK = 4mA,
SDAIN/SCLIN = 0.2V, VCC = 2.7V
2.7k to VCC on SDA, SCL, VCC = 3.3V,
Driven SDA, SCL = 0.1V
●
±5
●0
0.4
● 120
160
205
VILMAX
Buffer Input Logic Low Voltage
Timing Characteristics
fI2C,MAX
I2C Maximum Operating Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
VCC = 3.3V
(Note 3)
(Note 3)
●
1.2
400
600
1.3
tHD,STA
Hold Time After (Repeated) Start Condition (Note 3)
100
tSU,STA
Repeated Start Condition Set-Up Time
(Note 3)
0
tSU,STO
Stop Condition Set-Up Time
(Note 3)
0
tHD,DATI
Data Hold Time Input
(Note 3)
0
tSU,DAT
Data Set-Up Time
(Note 3)
100
UNITS
V
μA
μs
ns
ns
ns
V
μA
ns
ns
ns
mV
V
mV
pF
μA
V
mV
V
kHz
μs
ns
ns
ns
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See “Propagation Delays” in the Operations section for a
discussion of tPHL and tPLH as a function of pull-up resistance and bus
capacitance.
Note 3: Determined by design, not tested in production.
Note 4: Measure points are 0.3 • VCC and 0.7 • VCC.
Note 5: ICC test performed with connection circuitry active.
Note 6: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
43071fa
3
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