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H
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
mPD78062Y,78063Y,78064Y
Fig. 5-9 Serial Interface Channel 0 Block Diagram
Internal Bus
Selector
Serial I/O
Shift Register 0 (SIO0)
Output
Latch
Selector
Bus Release/Command/
Acknowledge Detector
Serial Clock Counter
Busy/Acknowledge
Output Circuit
Interrupt Request
Signal Generator
INTCSI0
Serial Clock Control Circuit
Selector
fXX/2-fXX/28
TO2
H
Fig. 5-10 Serial Interface Channel 2 Block Diagram
Internal bus
Receive Buffer
Register (RXB/SIO2)
Direction
Control Circuit
Direction
Control Circuit
Transmit Shift
Register (TXS/SIO2)
RXD/SI2/P70
TXD/SO2/P71
ASCK/SCK2/P72
Receive Shift
Register (RXS)
Receive
Control Circuit
Transmit
Control Circuit
INTST
INTSER
INTSR/INTCSI2
SCK Output
Control Circuit
Baud Rate
Generator
fXX-fXX/210
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