ST6210LB1/OTP 데이터 시트보기 (PDF) - STMicroelectronics

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ST6210LB1/OTP

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6208C/ST6209C/ST6210C/ST6220C

1 INTRODUCTION

The ST6208C, 09C, 10C and 20C devices are low

cost members of the ST62xx 8-bit HCMOS family

of microcontrollers, which is targeted at low to me-

dium complexity applications. All ST62xx devices

are based on a building block approach: a com-

mon core is surrounded by a number of on-chip

peripherals.

The ST62E20C is the erasable EPROM version of

the ST62T08C, T09C, T10C and T20C devices,

which may be used during the development phase

for the ST62T08C, T09C, T10C and T20C target

devices, as well as the respective ST6208C, 09C,

10C and 20C ROM devices.

OTP and EPROM devices are functionally identi-

cal. OTP devices offer all the advantages of user

programmability at low cost, which make them the

ideal choice in a wide range of applications where

frequent code changes, multiple code versions or

last minute programmability are required.

The ROM based versions offer the same function-

ality, selecting the options defined in the program-

Figure 1. Block Diagram

mable option bytes of the OTP/EPROM versions

in the ROM option list (See Section 11.6 on page

96).

The ST62P08C/P09C/P10C/P20C are the Factory

Advanced Service Technique ROM (FASTROM)

versions of ST62T08C, T09C, T10C and T20C

OTP devices.

They offer the same functionality as OTP devices,

but they do not have to be programmed by the

customer (See Section 11 on page 90).

These compact low-cost devices feature a Timer

comprising an 8-bit counter with a 7-bit program-

mable prescaler, an 8-bit A/D Converter with up to

8 analog inputs (depending on device) and a Dig-

ital Watchdog timer, making them well suited for a

wide range of automotive, appliance and industrial

applications.

For easy reference, all parametric data are located

in Section 11 on page 90.

8-BIT *

VPP

A/D CONVERTER

NMI

INTERRUPTS

P:ROGRAM

MEMORY

(1K, 2K

or 4K Bytes)

DATA ROM

USER

SELECTABLE

DATA RAM

64 Bytes

PORT A

PORT B

TIMER

PA0..PA3 (20mA Sink)

PB0..PB7 / Ain*

TIMER

PC

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

8-BIT CORE

POWER

SUPPLY

OSCILLATOR

RESET

VDD VSS OSCin OSCout RESET

* Depending on device. Please refer to I/O Port section.

WATCHDOG

TIMER

6/104

4

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