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MC74VHC1G125DFT2 Datasheet PDF : 6 Pages
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MC74VHC1G125
Noninverting 3−State Buffer
The MC74VHC1G125 is an advanced high speed CMOS
noninverting 3−state buffer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The MC74VHC1G125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G125 to be used to interface 5 V circuits to 3 V
circuits.
Features
• High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 58; Equivalent Gates = 15
• Pb−Free Packages are Available
OE 1
5 VCC
IN A 2
GND 3
4 OUT Y
Figure 1. Pinout (Top View)
OE
EN
IN A
OUT Y
Figure 2. Logic Symbol
http://onsemi.com
MARKING
DIAGRAMS
5
1
SC−88A/SOT−353/SC−70
DF SUFFIX
CASE 419A
5
W0 M G
G
1
5
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
5
W0 M G
G
1
W0 = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
OE
2
IN A
3
GND
4
OUT Y
5
VCC
A Input
L
H
X
FUNCTION TABLE
OE Input
Y Output
L
L
L
H
H
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
February, 2007 − Rev. 15
Publication Order Number:
MC74VHC1G125/D
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