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ICS8543I

Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

Renesas Electronics 

ICS8543I Data Sheet

LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

Inputs

OE

CLK_EN

0

X

1

0

1

0

1

1

1

1

CLK_SEL

X

0

1

0

1

Selected Source

CLK/nCLK

PCLK/nPCLK

CLK/nCLK

PCLK/nPCLK

Outputs

Q0:Q3

nQ0:nQ3

Hi-Z

Hi-Z

Disabled; Low

Disabled; High

Disabled; Low

Disabled; High

Enabled

Enabled

Enabled

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.

nCLK, nPCLK

CLK, PCLK

CLK_EN

Disabled

Enabled

nQ0:nQ3

Q0:Q3

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

Inputs

CLK or PCLK nCLK or nPCLK

0

1

1

0

0

Biased; NOTE 1

1

Biased; NOTE 1

Biased; NOTE 1

0

Biased; NOTE 1

1

Outputs

Q[0:3]

nQ[0:3]

LOW

HIGH

HIGH

LOW

LOW

HIGH

HIGH

LOW

HIGH

LOW

LOW

HIGH

Input to Output Mode

Differential to Differential

Differential to Differential

Single-Ended to Differential

Single-Ended to Differential

Single-Ended to Differential

Single-Ended to Differential

Polarity

Non-Inverting

Non-Inverting

Non-Inverting

Non-Inverting

Inverting

Inverting

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

ICS8543BGI REVISION E NOVEMBER 15, 2012

3

©2012 Integrated Device Technology, Inc.

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