ICS8543I 데이터 시트보기 (PDF) - Renesas Electronics
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ICS8543I Datasheet PDF : 18 Pages
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ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
3
Name
GND
CLK_EN
CLK_SEL
Type
Power
Input
Pullup
Input
Pulldown
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects PCLK/nPCLK inputs.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
4
5
6
7
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK
nCLK
PCLK
nPCLK
OE
VDD
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8543BGI REVISION E NOVEMBER 15, 2012
2
©2012 Integrated Device Technology, Inc.
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