CY7C1443AV33 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1443AV33 Datasheet PDF : 31 Pages
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Pin Definitions
Name
A0, A1, A
BWA, BWB
BWC, BWD,
BWE, BWF,
BWG, BWH
GW
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ADSC
BWE
ZZ
DQs
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
I/O-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless
of the values on BWX and BWE).
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is
ignored if CE1 is HIGH. CE1 is sampled only when a new external address is
loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled
only when a new external address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. CE3 is
assumed active throughout this document for BGA. CE3 is sampled only when
a new external address is loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK,
active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A[1:0] are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH
Address Strobe from Controller, sampled on the rising edge of CLK,
active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers.
When ADSP and ADSC are both
Aas[1s:0e]ratered,aolsnolyloAaDdeSdPinistorethceogbnuirzsetdc.ounter.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQPX are placed in a tri-state condition.The outputs are automati-
cally tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Document #: 38-05357 Rev. *F
Page 7 of 31
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