CY7C1443AV33 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1443AV33 Datasheet PDF : 31 Pages
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Truth Table[2, 3, 4, 5, 6]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
100
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Cycle Description
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADDRESS
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE1 CE2 CE3 ZZ ADSP
H X XL X
L L XL L
L X HL L
L L XL H
X X XL H
X X XH X
L H LL L
L H LL L
L H LL H
L H LL H
L H LL H
X X XL H
X X XL H
H X XL X
H X XL X
X X XL H
H X XL X
X X XL H
X X XL H
H X XL X
H X XL X
X X XL H
H X XL X
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV WRITE OE CLK
X
X X L-H
X
X X L-H
X
X X L-H
X
X X L-H
X
X X L-H
X
X XX
X
X L L-H
X
X H L-H
X
L X L-H
X
H L L-H
X
H H L-H
L
H L L-H
L
H H L-H
L
H L L-H
L
H H L-H
L
L X L-H
L
L X L-H
H
H L L-H
H
H H L-H
H
H L L-H
H
H H L-H
H
L X L-H
H
L X L-H
DQ
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Tri-State
D
D
Q
Tri-State
Q
Tri-State
D
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05357 Rev. *F
Page 10 of 31
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