ADSP-21367KBPZ-3A(RevG) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21367KBPZ-3A Datasheet PDF : 62 Pages
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ADSP-21367/ADSP-21368
The serial ports also contain frame sync error detection logic
Serial Peripheral (Compatible) Interface
where the serial ports detect frame syncs that arrive early (for
example, frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
The processors contain two serial peripheral interface ports
(SPIs). The SPI is an industry-standard synchronous serial link,
enabling the SPI-compatible port to communicate with other
SPI-compatible devices. The SPI consists of two data pins, one
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left-justified, I2S, or
right-justified with word widths of 16, 18, 20, or 24 bits.
device select pin, and one clock pin. It is a full-duplex
synchronous serial interface, supporting both master and slave
modes. The SPI port can operate in a multimaster environment
by interfacing with up to four other SPI-compatible devices,
either acting as a master or slave device. The ADSP-21367/
ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-
mentation also features programmable baud rate and clock
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
or the sample rate converters (SRC) and are controlled by the
E SRU control registers.
Synchronous/Asynchronous Sample Rate Converter
The sample rate converter (SRC) contains four SRC blocks and
T is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 128 dB
SNR. The SRC block is used to perform synchronous or asyn-
chronous sample rate conversion across independent stereo
E channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to con-
vert multichannel audio data without phase mismatches.
Finally, the SRC can be used to clean up audio data from jittery
L clock sources such as the S/PDIF receiver.
Input Data Port
The IDP provides up to eight serial input channels—each with
O its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
S audio channels in I2S, left-justified sample pair, or right-justi-
fied mode. One frame sync cycle indicates one 64-bit left/right
pair, but data is sent to the FIFO as 32-bit words (that is, one-
half of a frame at a time). The processor supports 24- and 32-bit
B I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit
right-justified formats.
Precision Clock Generators
O The precision clock generators (PCG) consist of four units, each
phase and polarities. The SPI-compatible port uses open-drain
drivers to support a multimaster configuration and to avoid
data contention.
UART Port
The processors provide a full-duplex universal asynchronous
receiver/transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for five data bits
to eight data bits, one stop bit or two stop bits, and none, even,
or odd parity. The UART port supports two modes of
operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 bits to 12 bits per frame.
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
Where the 16-bit UART_Divisor comes from the DLH register
(most significant eight bits) and DLL register (least significant
eight bits).
Digital Peripheral Interface (DPI)
In conjunction with the general-purpose timer functions, auto-
The digital peripheral interface provides connections to two
baud detection is supported.
serial peripheral interface ports (SPI), two universal asynchro-
nous receiver-transmitters (UARTs), a 2-wire interface (TWI),
12 flags, and three general-purpose timers.
Rev. G | Page 9 of 62 | September 2017
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