ADSP-21367KSWZ-1A(RevG) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21367KSWZ-1A Datasheet PDF : 62 Pages
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ADSP-21367/ADSP-21368
The block diagram of the ADSP-21368 on Page 1 also shows the
• Digital peripheral interface that includes three timers, a 2-
peripheral clock domain (also known as the I/O processor) and
wire interface, two UARTs, two serial peripheral interfaces
contains the following features:
(SPI), 2 precision clock generators (PCG) and a flexible sig-
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
nal routing unit (DPI SRU).
buses for 32-bit data transfers
SHARC FAMILY CORE ARCHITECTURE
• Peripheral and external port buses for core connection
The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-
• External port with an AMI and SDRAM controller
ble at the assembly level with the ADSP-2126x, ADSP-21160,
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21367/ADSP-21368/
ADSP-21369 processors share architectural features with the
• Digital applications interface that includes four precision
ADSP-2126x and ADSP-2116x SIMD SHARC processors, as
clock generators (PCG), a input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
shown in Figure 2 and detailed in the following sections.
S TE SIMD Core
DMD/PMD 64
E DAG1
OL 16x32
DAG2
16x32
JTAG FLAG TIMER INTERRUPT CACHE
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
PM DATA 48
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
S MULTIPLIER SHIFTER ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ALU
SHIFTER MULTIPLIER
B MRF
O80-BIT
MRB
80-BIT
ASTATx
ASTATy
MSB
80-BIT
MSF
80-BIT
STYKx
STYKy
Figure 2. SHARC Core Block Diagram
Rev. G | Page 4 of 62 | September 2017
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