ADSP-21367KSWZ-1A(RevG) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21367KSWZ-1A Datasheet PDF : 62 Pages
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ADSP-21367/ADSP-21368
Peripheral Timers
Delay Line DMA
Three general-purpose timers can generate periodic interrupts
The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-
and be independently set to operate in one of three modes:
vide delay line DMA functionality. This allows processor reads
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
and writes to external delay line buffers (in external memory,
SRAM, or SDRAM) with limited core interaction.
SYSTEM DESIGN
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu-
The following sections provide an introduction to system design
options and power supply issues.
ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
Program Booting
register enables or disables all three general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
E The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multimaster data
T arbitration
• Digital filtering and timed event processing
• 7-bit and 10-bit addressing
E • 100 kbps and 400 kbps data rates
• Low interrupt rate
I/O PROCESSOR FEATURES
L The I/O processor provides many channels of DMA, and con-
trols the extensive set of peripherals described in the previous
sections.
O DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
S DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
B (input data port), the parallel data acquisition port (PDAP), or
the UART.
Thirty four channels of DMA are available on the ADSP-2136x
O processors as shown in Table 6.
The internal memory of the processors can be booted up at sys-
tem power-up from an 8-bit EPROM via the external port, an
SPI master or slave, or an internal boot. Booting is determined
by the boot configuration (BOOT_CFG1–0) pins (see Table 7
and the processor hardware reference). Selection of the boot
source is controlled via the SPI as either a master or slave device,
or it can immediately begin executing from ROM.
Table 7. Boot Mode Selection
BOOT_CFG1–0
00
01
10
11
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
No boot (processor executes from
internal ROM after reset)
Power Supplies
The processors have separate power supply connections for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power
supplies. The internal and analog supplies must meet the 1.3 V
requirement for the 400 MHz device and 1.2 V for the
333 MHz and 266 MHz devices. The external supply must meet
the 3.3 V requirement. All external supply pins must be con-
nected to the same power supply.
Note that the analog supply pin (AVDD) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
AVDD pin. Place the filter components as close as possible to the
AVDD/AVSS pins. For an example circuit, see Figure 3. (A recom-
mended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDDINT and GND. Use wide traces
to connect the bypass capacitors to the analog power (AVDD) and
Table 6. DMA Channels
ground (AVSS) pins. Note that the AVDD and AVSS pins specified in
Figure 3 are inputs to the processor and not the analog ground
Peripheral
SPORTs
DMA Channels
16
plane on the board—the AVSS pin should connect directly to dig-
ital ground (GND) at the chip.
PDAP
8
SPI
2
UART
4
External Port
2
Memory-to-Memory
2
Rev. G | Page 10 of 62 | September 2017
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