SCY99080CDWR2G 데이터 시트보기 (PDF) - ON Semiconductor

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SCY99080CDWR2G

High Performance Switch-Mode Power Supply Controller for Backlight and LLC Converters

ON Semiconductor 

Pulse

Trigger

Level

Shifter

DDA002C

S

Q

R

Q

Boot

Hgd

CBOOT

VBULK

from EN2

B

A

from latch

high if OK

UV

Detect

DELAY

HB

Vcc

Lgd

Gnd

DBOOT

Vaux

Figure 57. The Internal Lgd and Hgd Driver Section of the DDA002C

The A and B outputs are delivered by the internal logic, as

depicted in VCO block diagram. This logic is constructed in

such a way that the Lgd driver starts to pulse first after any

controller restart. The bootstrap capacitor is thus charged

during first pulse. A delay is included in the lower rail to

ensure good matching between these propagating signals. As

stated in the maximum rating section, the floating portion can

go up to 600 VDC and makes the IC perfectly suitable for

offline applications featuring a 400 V PFC front−end stage.

The Synchronization Outputs (Lgs and Hgs)

In addition to the power drivers, this IC features two

ground referenced low power synchronization outputs that

can be used to drive second power driver (in full bridge

applications) or to trigger synchronous rectification

circuitry via isolation transformer. On−time of the

synchronization outputs can be easily clamped to needed

value using a single resistor connected from the Dgs pin to

ground. Maximum feasible on−time of the synchronization

outputs is never higher than the on−time of the power

outputs. Please refer to Figures 35 and 37 for more details on

how the synchronization output signals are generated. The

selection table for the Rdgs resistor that dictates the

maximum on−time on the Lgs ang Hgs outputs can be seen

in Figure 58.

19

17

15

13

11

9

7

5

10 15 20 25 30 35 40 45 50 55

Rdgs (kW)

Figure 58. On Time Clamp Selection Chart

Layout Recommendations

The DDA002C contains sensitive inputs that uses high

resistance resistors (depends on desired operating frequency

range, deadtime and sync outputs on time clamp duration).

Mentioned high impedance inputs can be sensitive to noise

generated by HB and/or driver pins. Care thus has to be taken

during SMPS layout design. Please refer to Figure 59 for

recommended layout.

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