ISL97687
4. The relatively quiet AGND area, to the right of the neck needs
to be traced out carefully in unbroken metal, via the shortest
possible path to the ground side of the components
connected to OVP, COMP, ISET, PWM_SET/PLL, and ACTL. This
is also true for the filtering caps on PWMI and STV. These are
needed to reject noise and cause decoding errors in some
conditions.
5. The current sensing line is shielded by a metal trace, coming
from its source, to prevent pickup from the GD pin beside it.
PVIN
PGND
6. The filtering cap of the current sensing line should be placed
close to the CS pin rather than in the area of current sense
resistor, as it needs to couple this pin to the adjacent PGND pin.
7. The noisy switching FET should be kept far away from the
quiet pin area.
8. The area on the switching node should be determined by the
dissipation requirements of the boost power FET.
PIN 1
INDUCTOR
VOUT
DIODE
PGND
FIGURE 29. EXAMPLE OF TWO LAYER PCB LAYOUT
FN7714 Rev.3.00
Sep 13, 2017
Page 19 of 24