DS2153Q 데이터 시트보기 (PDF) - Maxim Integrated

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DS2153Q

E1 Single-Chip Transceiver

Maxim Integrated 

DS2153Q

4 CONTROL AND TEST REGISTERS

The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers

are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the

control registers only need to be accessed when there is a change in the system configuration. There are

two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2),

and three Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described

in this section. The LICR is described in Section 13.

The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On power-

up, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly.

RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10B Hex)

(MSB)

RSMF

RSM

RSIO

—

—

FRC

SYNCE

(LSB)

RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

RSMF

RSM

RSIO

—

—

FRC

SYNCE

RESYNC

RCR1.7

RCR1.6

RCR1.5

RCR1.4

RCR1.3

RCR1.2

RCR1.1

RCR1.0

RSYNC Multiframe Function. Only used if the RSYNC pin is

programmed in the multiframe mode (RCR1.6 = 1).

0 = RSYNC outputs CAS multiframe boundaries

1 = RSYNC outputs CRC4 multiframe boundaries

RSYNC Mode Select.

0 = frame mode (see the timing in Section 14)

1 = multiframe mode (see the timing in Section 14)

RSYNC I/O Select.

0 = RSYNC is an output (depends on RCR1.6)

1 = RSYNC is an input (only valid if elastic store enabled) (Note:

this bit must be set to 0 when RCR2.1 = 0)

Not Assigned. Should be set to 0 when written.

Not Assigned. Should be set to 0 when written.

Frame Resync Criteria.

0 = resync if FAS received in error 3 consecutive times

1 = resync if FAS or bit 2 of non-FAS is received in error 3

consecutive times

Sync Enable.

0 = auto resync enabled

1 = auto resync disabled

Resync. When toggled from low to high, a resync is initiated. Must

be cleared and set again for a subsequent resync.

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