DS2153Q 데이터 시트보기 (PDF) - Maxim Integrated

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DS2153Q

E1 Single-Chip Transceiver

Maxim Integrated 

DS2153Q

Table 4-1. Sync/Resync Criteria

FRAME OR

MULTIFRAME

LEVEL

FAS

SYNC CRITERIA

FAS present in frames N

and N + 2, and FAS not

present in frame N + 1.

CRC4

Two valid MF alignment

words found within 8ms.

RESYNC CRITERIA

Three consecutive incorrect FAS received.

Alternate (RCR1.2 = 1) the above criteria

is met or three consecutive incorrect bit 2

of non-FAS received.

915 or more CRC4 codewords out of 1000

received in error.

Valid MF alignment word Two consecutive MF alignment words

CAS

found and previous time slot received in error.

16 contains code other than

all 0s.

ITU SPEC

G.706

4.1.1

4.1.2

G.706

4.2

4.3.2

G.732

5.2

RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)

(MSB)

Sa8S

Sa7S

Sa6S

Sa5S

Sa4S RSCLKM RESE

(LSB)

—

SYMBOL

POSITION NAME AND DESCRIPTION

Sa8S

RCR2.7

Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;

set to 0 to not report the Sa8 bit.

Sa7S

RCR2.6

Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin;

set to 0 to not report the Sa7 bit.

Sa6S

RCR2.5

Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;

set to 0 to not report the Sa6 bit.

Sa5S

RCR2.4

Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;

set to 0 to not report the Sa5 bit.

Sa4S

RCR2.3

Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;

set to 0 to not report the Sa4 bit.

RSCLKM

RCR2.2

Receive Side SYSCLK Mode Select.

0 = if SYSCLK is 1.544MHz

1 = if SYSCLK is 2.048MHz

RESE

RCR2.1

Receive Side Elastic Store Enable.

0=elastic store is bypassed

1=elastic store is enabled

—

RCR2.0 Not Assigned. Should be set to 0 when written.

11 of 60

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