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ICSSSTV16857C

DDR 14-Bit Registered Buffer

Integrated Circuit Systems 

ICSSSTV16857C

General Description

The 14-bit ICSSSTV16857C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels,

except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge

of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an

LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power

standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic

“Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always

be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.

To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic

“Low” level during power up.

In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.

Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,

the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the

differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power

standby state, the register will become active quickly relative to the time to enable the differential input receivers. When

the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the

input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.

Pin Configuration

PIN NUMBER

24, 23, 20, 19, 18,

15, 14, 11, 10, 7,

6, 5, 2, 1

3, 8, 13, 22,

27, 36, 46

4, 9, 12, 16, 21

25, 26, 29, 30, 31,

32, 33, 40, 41, 42,

43, 44, 47, 48

38

39

28, 37, 45

34

35

PIN NAME

Q (14:1)

GND

VDDQ

D (14:1)

CLK

CLK#

VDD

RESET#

VREF

TYPE

OUTPUT

Data output

DESCRIPTION

PWR

PWR

INPUT

INPUT

INPUT

PWR

INPUT

INPUT

Ground

Output supply voltage

Data input

Positive clock input

Negative clock input

Core supply voltage

Reset (active low)

Input reference voltage

0002F—10/25/02

2

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