ICSSSTV16857C 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICSSSTV16857C Datasheet PDF : 8 Pages
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Integrated
Circuit
Systems, Inc.
DDR 14-Bit Registered Buffer
ICSSSTV16857C
Recommended Applications:
• DDR Memory Modules
• Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
• SSTL_2 compatible data registers
Product Features:
• Differential clock signal
• Meets SSTL_2 signal data
• Supports SSTL_2 class I & II specifications
• Low-voltage operation
- VDD = 2.3V to 2.7V
• 48 pin TSSOP package
Truth Table1
Inputs
RESET# CLK
CLK#
L
X or
X or
Floating Floating
H
↑
↓
H
↑
↓
H
L or H L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q0(2)
Pin Configuration
Q1
1
Q2
2
GND
3
VDDQ
4
Q3
5
Q4
6
Q5
7
GND
8
VDDQ
9
Q6
10
Q7
11
VDDQ
12
GND
13
Q8
14
Q9
15
VDDQ
16
GND
17
Q10
18
Q11
19
Q12
20
VDDQ
21
GND
22
Q13
23
Q14
24
48
D1
47
D2
46
GND
45
VDD
44
D3
43
D4
42
D5
41
D6
40
D7
39
CLK#
38
CLK
37
VDD
36
GND
35
VREF
34
RESET#
33
D8
32
D9
31
D10
30
D11
29
D12
28
VDD
27
GND
26
D13
25
D14
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
Block Diagram
CLK
CLK#
38
39
RESET# 34
D1
VREF
48
35
R
CLK
D1
1 Q1
0002F—10/25/02
To 13 Other Channels
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