MAX188ACAP(2012) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX188ACAP Datasheet PDF : 25 Pages
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MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Table 3. Channel Selection in Single-Ended Mode (SGL/DIFF = 1)
SEL2
0
1
0
1
0
1
0
1
SEL1
0
0
0
0
1
1
1
1
SEL0
0
0
1
1
0
0
1
1
CH0
+
CH1
+
CH2
+
CH3 CH4
+
+
CH5
+
CH6
+
CH7
+
AGND
–
–
–
–
–
–
–
–
Table 4. Channel Selection in Differential Mode (SGL/DIFF = 0)
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CH0
+
–
CH1
–
+
CH2
+
–
CH3
–
+
CH4
+
–
CH5
–
+
CH6 CH7
+
–
–
+
2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX186/MAX188 low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB3.
6) Pull CS on the MAX186/MAX188 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of dead time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital Output
In unipolar input mode, the output is straight binary
(see Figure 15). For bipolar inputs, the output is
twos-complement (see Figure 16). Data is clocked out
at the falling edge of SCLK in MSB-first format.
Maxim Integrated
11
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