CXD1910AQ
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
fSYSCLK
tPWHCLK
tPWLCLK
SYSCLK
PDCLK
VSYNC,
HSYNC,
FID
tPDCLKD
tOD
tOH
tPDCLKD
Item
SYSCLK clock rate
SYSCLK pulse width Low
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
Symbol
fSYSCLK
tPWLCLK
tPWHCLK
tPDCLKD
tCOD
tCOH
Min.
11
11
3
Typ.
27
Max.
20
25
Unit
MHz
ns
ns
ns
ns
ns
–9–