CXD1910AQ 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD1910AQ Datasheet PDF : 28 Pages
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CXD1910AQ
Pin
No.
Symbol I/O
Description
30 AVDD3
— Analog power supply
31 AVSS3
— Analog ground
32 C-OUT/U
This is the output of 10-bit D/A converter.
When control register bit “YC/YUV” = “1”:
O
This pin outputs chroma (C) signal.
When control register bit “YC/YUV” = “0”:
This pin outputs color difference (U) signal.
33 TD10
Test data bus.
I/O
This pin should be open.
When test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
34 VDD
35 TD9
36 TD8
— Digital power supply
I/O Test data bus.
These pins should be open.
I/O
When test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
37 XTEST1
38 XTEST2
39 XTEST3
I Test mode control input pins. These pins are pulled up.
I When these pins are “H”, the CXD1910AQ is not test mode.
I Test mode is available only for device bender.
40 VSS
41 TRST
— Digital ground
I
Test mode reset input pins.
When power on reset, set “L” for more than 40 clocks (SYSCLK).
42 VDD
— Digital power supply
43 TDI
I Test mode control input pins. This pin is pulled up.
44 TMS
I Test mode control input pins. This pin is pulled up.
45 TCK
I Test mode control input pins. This pin should be “H” input.
46 TDO
O Test data bus. This pin should be open.
47 VSS
48 SI/SDA
— Digital ground
This pin's function is selected by XIICEN (Pin 64).
I When XIICEN = “H”, this pin is SONY SIO mode; SI serial data input.
When XIICEN = “L”, this pin is I2C-BUS mode; SDA input/output.
49 SCK/SCL
This pin's function is selected by XIICEN (Pin 64).
I When XIICEN = “H”, this pin is SONY SIO mode; SCK serial clock input.
When XIICEN = “L”, this pin is I2C-BUS mode; SCL input.
50 XCS/SA
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; XCS chip select input.
I When XIICEN = “L”, this pin is I2C-BUS mode; SA slave address select input
signal which selects I2C-BUS slave address.
51 XVRST
Vertical sync reset input pin in active low. This pin is pulled up.
I This is used to synchronize external vertical sync and internal vertical sync.
When XVRST is “L”, internal digital sync generator is reset according to F1 status.
–4–
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