CXD2464R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2464R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2464R

(B) HP7, 6, 5, 4, 3, 2, 1, 0

These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment

of up to 256 clk with 8 bits is possible using the front edge of HSYNC as the reference.

HSYNC

Thp

Image display period

Thp: Timing from the edge of HSYNC to the start of image display

Minimum and maximum Thp setting values for each mode

LCX026

HP 7 6 5 4 3 2 1 0 800 × 600 762 × 572 640 × 480 640 × 400

Min. H H H H H H H H 161 clk

115 clk

Max. L L L L L L L L 416 clk

370 clk

LCX016

HP 7 6 5 4 3 2 1 0 832 × 624 800 × 600 762 × 572 640 × 480 640 × 400 832 × 480

Min. H H H H H H H H 185 clk 155 clk

109 clk

Max. L L L L L L L L 440 clk 410 clk

364 clk

LCX012BL

HP 7 6 5 4 3 2 1 0 644 × 484

Min. H H H H H H H H 112 clk

Max. L L L L L L L L 367 clk

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