CXD2464R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2464R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2464R

Each control data is described in detail below. (A) to (M)

(A) PLLP10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The

data is 11 bits and the frequency division ratio can be set up to 2048. The actual frequency division ratio

should be set as follows.

Number of clk for the horizontal period – 2 = Actual number of dots set

Examples of settings for major modes are shown below.

Examples using the LCX026

1) SVGA (800 × 600)

PLLP setting value = 1040 (horizontal period) – 2 → 1038 (HLLLLLLHHHL: LSB)

PLLP 10 9 8 7 6 5 4 3 2 1 0

Setting data H L L L L L L H H H L

∗ VESA SVGA72

2) VGA (640 × 480)

PLLP setting value = 832 (horizontal period) – 2 → 830 (LHHLLHHHHHL: LSB)

PLLP 10 9 8 7 6 5 4 3 2 1 0

Setting data L H H L L H H H H H L

∗ VESA VGA72

3) PC-98 (640 × 400)

PLLP setting value = 848 (horizontal period) – 2 → 846 (LHHLHLLHHHL: LSB)

PLLP 10 9 8 7 6 5 4 3 2 1 0

Setting data L H H L H L L H H H L

4) NTSC (640 × 480)

PLLP setting value = 1560 (horizontal period) – 2 → 1558 (HHLLLLHLHHL: LSB)

PLLP 10 9 8 7 6 5 4 3 2 1 0

Setting data H H L L L L H L H H L

5) PAL (762 × 572)

PLLP setting value = 1880 (horizontal period) – 2 → 1878 (HHHLHLHLHHL: LSB)

PLLP 10 9 8 7 6 5 4 3 2 1 0

Setting data H H H L H L H L H H L

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