CXD3500R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

Pin

No.

Symbol

34 VST

35 TEST8

36 PCG

37 DWN

38 ENB2

39 CLP

40 VSS2

41 TEST9

42 PRG

43 FRP

44 XFRP

45 SHP1A

46 SHP1B

47 SHP2A

48 SHP2B

49 INV

50 XVS

51 XHS

52 IRACT

53 ORACT

54 RSTR

55 VSS3

56 VDD1

57 RCK

58 RSTW

59 WCK

60 SCTR

61 SCLK

62 SDAT

63 HDN

64 CKI1

I/O

Description

O Vertical display start pulse output

— Test (Not connected.)

O Precharge timing pulse output

O Up/down inversion discrimination signal output (H: Down, L: Up)

O ENB2 pulse output

O Pedestal clamp pulse output for CXA2112R

— GND

— Test (Not connected.)

O Precharge signal pulse output

O AC drive inversion timing output

O AC drive inversion timing output (reverse polarity of FRP)

O External sample-and-hold driver control signal (for CXA2112R)

O External sample-and-hold driver control signal (for CXA2112R)

O External sample-and-hold driver control signal (for CXA2112R)

O External sample-and-hold driver control signal (for CXA2112R)

O External sample-and-hold driver control signal (for CXA2112R)

O Vertical auxiliary pulse output

O Horizontal auxiliary pulse output

O LAP control pulse output

O LAP control pulse output

O Reset read output (for high-speed line buffer)

— GND

— VDD

O Read clock output (for high-speed line buffer)

O Reset write output (for high-speed line buffer)

O Write clock output (for high-speed line buffer)

I Chip select input (serial transfer block)

I Serial clock input (serial transfer block)

I Serial data input (serial transfer block)

O Phase comparator pulse output

I Clock 1 input (TTL)

Input pin for

open status

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∗ H: Pull up

–4–

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