CXD3500R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

Pin Description

Pin

No.

Symbol

1 HSYNC

2 VSYNC

3 CKI2

4 CKLIM

5 VD

6 FLD

7 TEST0

8 VSS0

9 TEST1

10 RGTCNT

11 FRPCNT

12 TEST2

13 TEST3

14 TEST4

15 TEST5

16 TEST6

17 CKI3

18 TEST7

19 XCLR

20 MODE3

21 MODE2

22 MODE1

23 VSS1

24 VDD0

25 RGT

26 XRGT

27 HST

28 HCK1

29 HCK2

30 BLK

31 HD

32 ENB1

33 VCK

I/O

Description

Input pin for

open status

I Horizontal sync signal input

—

I Vertical sync signal input

—

I/O Clock 2 input (Small signal: Vth = VDD/2, min. Vp-p = 0.5V)

—

I Clock input selector (CKI1 selected when open.)

H

O VD pulse output

—

I/O FLD pulse I/O

—

— Test (Not connected.)

—

— GND

—

— Test (Not connected.)

—

I Right/left inversion external control

—

I FRP pulse inversion external control

H

— Test (Not connected.)

—

— Test (Not connected.)

—

— Test (Not connected.)

—

— Test (Not connected.)

—

— Test (Connect to GND.)

—

I Clock 3 input (for LAP)

—

— Test (Not connected.)

H

I System clear (L: set to SVGA 60Hz)

H

O Parallel Out 3 output (Panel mode switching 3 output)

—

O Parallel Out 2 output (Panel mode switching 2 output)

—

O Parallel Out 1 output (Panel mode switching 1 output)

—

— GND

—

— VDD

—

O Right/left inversion discrimination signal output (H: Normal, L: Reverse)

—

O Right/left inversion discrimination signal output (reverse polarity of RGT) —

O Horizontal display start pulse output

—

O Horizontal display clock pulse output

—

O Horizontal display clock pulse output

—

O BLK pulse output

—

O HD pulse output

—

O ENB1 pulse output

—

O Vertical display clock pulse output

—

∗ H: Pull up

–3–

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