HMP8112A 데이터 시트보기 (PDF) - Harris Semiconductor

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HMP8112A

NTSC/PAL Video Decoder

Harris Semiconductor 

HMP8112A

BIT

NUMBER

FUNCTION

7-0

DC RESTORE

END Time (LSB)

TABLE 26. DC RESTORE END TIME (LSB) REGISTER

SUB ADDRESS = 0x14

DESCRIPTION

RESET

STATE

This register provides a programmable delay for the internal DC RESTORE signal. This 0101 0010B

is the lower byte of the 10-bit word.

(0x52)

BIT

NUMBER

FUNCTION

15 - 10 Not Used

9-8

DC RESTORE

END Time (MSB)

TABLE 27. DC RESTORE END TIME (MSB) REGISTER

SUB ADDRESS = 0x15

DESCRIPTION

RESET

STATE

Write Ignored, Read 0’s

This register provides a programmable delay for the internal DC RESTORE signal. This

is the upper byte of the 10-bit word.

0000 0000B

(0x00)

TABLE 28. OUTPUT FORMAT CONTROL REGISTER

SUB ADDRESS = 0x16

BIT

NUMBER

FUNCTION

DESCRIPTION

7

Square Pixel/ITU-R When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected.

BT601 Select

6, 5, 4

Output Field Control These bits control the field capture rate of the HMP8112A. The user can select every 4th

“FLD_CONT(2-0)” field, every other field or every field of video to be output to the data port.

000 = No Capture Enabled

001 = Capture every 4th field

010 = Capture every 2nd field

011 = Capture every 2nd odd field

100 = Capture every 2nd even field

101 = Capture every odd field

110 = Capture every even field

111 = Capture all fields

3

8/16 output Select When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchro-

nous Pixel Transfer output mode is selected.

2

OEN

This bit enables the Y(7-0), CbCr(7-0), ACTIVE, FIELD, HSYNC, VSYNC and DVLD out-

puts. 1 = Outputs enabled; 0 = three-stated.

1

Vertical Pixel Siting When this bit is cleared (‘0’) the chrominance pixels have a 1/2 line pixel offset from their

associated luminance pixel in a 4:2:2 subsampled scheme. When this bit is set (‘1’) the

pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. The

bit is cleared by a RESET.

0

Not Used

Write Ignored, Read 0’s

RESET

STATE

0B

000B

0B

0B

0B

0B

4-20

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