SL74HC161 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74HC161 Datasheet PDF : 9 Pages
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SL74HC161
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
fmax
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tTLH, tTHL
CIN
VCC
Parameter
V
Maximum Clock Frequency (Figures 1,6)
2.0
4.5
6.0
2.0
4.5
Maximum Propagation Delay Clock to Q
6.0
(Figures 1,6)
2.0
4.5
6.0
Maximum Propagation Delay Reset to Q
2.0
(Figures 2 and 6)
4.5
6.0
2.0
4.5
Maximum Propagation Delay Enable T to Ripple 6.0
Carry Out
(Figures 3,6)
2.0
4.5
6.0
2.0
4.5
Maximum Propagation Delay Clock to Ripple
6.0
Carry Out (Figures 1,6)
2.0
4.5
6.0
Maximum Propagation Delay Reset to Ripple Carry 2.0
Out (Figures 2,6)
4.5
6.0
Maximum Output Transition Time, Any Output
2.0
(Figures 1 and 6)
4.5
6.0
Maximum Input Capacitance
-
Guaranteed Limit
25 °C to ≤85°C ≤125°C
-55°C
6
5
4
30
24
20
35
28
24
120
160
200
20
23
28
16
20
22
145
185
320
22
25
30
18
20
23
145
185
220
20
22
25
17
19
21
110
150
190
16
18
20
14
15
17
135
175
210
18
20
22
15
16
20
120
160
200
22
27
30
18
22
25
145
185
220
22
28
35
20
24
28
155
190
230
22
26
30
18
22
25
75
95
110
15
19
22
13
16
19
10
10
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Power Dissipation Capacitance (Per Gate)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
30
pF
SLS
System Logic
Semiconductor
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