74VCX08(2013) 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74VCX08
(Rev.:2013)

Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs

Fairchild Semiconductor 

0.43TYP

14

“

A

8

B

0.65

6.4

“

6.10

3.2

1.65

PIN#1 IDENT

1

TOP VIEW

7

0.2 C B A

ALL LEAD TIPS

0.45

RECOMMENDED LAND PATTERN

1.2 MAX

0.90+-00..1105

“

SEE DETAIL A

0.20

0.09

ALL LEAD TIPS

0.1 C

0.65

0.30

0.19

C

0.13 A B C

FRONT VIEW

ƒ723 %27720

NOTES:

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS ARE EXCLUSIVE OF BURRS,

ƒƒ

MOLD FLASH, AND TIE BAR EXTRUSIONS

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 2009.

E. LANDPATTERN STANDARD: SOP65P640X110-14M.

F. DRAWING FILE NAME: MKT-MTC14rev7.

0.09 MIN

0.09 MIN

“

1.00

DETAIL A

GAGE PLANE

0.25

SEATING PLANE

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