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MJW16110 Datasheet PDF : 10 Pages
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MJ16110 MJW16110
DYNAMIC SATURATION VOLTAGE
For bipolar power transistors low DC saturation voltages
are achieved by conductivity modulating the collector region.
+ 24
Since conductivity modulation takes a finite amount of time,
DC saturation voltages are not achieved instantly at turn–on.
In bridge circuits, two transistor forward converters, and two
transistor flyback converters dynamic saturation characteris-
tics are responsible for the bulk of dynamic losses. The
MJ16110 has been designed specifically to minimize these
losses. Performance is roughly four times better than the
original version of MJ16010.
Q1 MJ11012
1k
1N5314
48
100
µF
1k 7
1N4111
10 k
U1
6
MC1455
(OSCILLATOR)
100 pF
3
2
Q4
IRFD9120
2.4 Ω
20 W
100 Ω
1W
0.01 µF
2.4 mH
Q5
MTM8P08
1N5831
From a measurement point of view, dynamic saturation
voltage is defined as collector–emitter voltage at a specific
point in time after IB1 has been applied, where t = 0 is the
90% point on the IB1 rise time waveform, This definition is il-
lustrated in Figure 11. Performance data was taken in the cir-
cuit that is shown in Figure 13. The 24 volt rail allows a
Tektronix 2445 or equivalent scope to operate at 1 volt per
division without input amplifier saturation.
Dynamic saturation performance is illustrated in Figure 12.
The MJ16110 reaches DC saturation levels in approximately
2 µs, provided that sufficient base drive is provided. The de-
pendence of dynamic saturation voltage upon base drive
0.1 µF
1N914
10 k
2
15
0.01 µF
47 Ω
48
1W
1.8 k
IRFD9123
7
500 Ω
6
Q2
3
15
0.01 µF
0.01 µF
Q3
IRFD113
10 µF
MUR405 I B
MUR405
Q6
MTP25N06
IC
V CE
suggests a spike of IB1 at turn–on to minimize dynamic satu-
ration losses, and also avoid overdrive at turn–off. However,
in order to simulate worst case conditions the guaranteed dy-
Figure 13. Dynamic Saturation Test Circuit
namic saturation limits in this data sheet are specified with a
constant level of IB1.
GUARANTEED SAFE OPERATING AREA INFORMATION
50 TC = 25°C
20
10
MJ16110
10 µs
5
MJW16110
3
2
REGION II —
1
EXPANDED FBSOA USING
MUR870 ULTRA-FAST
100
1 ms
ns
0.5
0.3
RECTIFIER, SEE FIGURE 16
dc
0.2
II
0.1
BONDING WIRE LIMIT
0.05
THERMAL LIMIT
0.03
SECONDARY BREAKDOWN
0.02
LIMIT
0.01
1
23 5
10 20 30 50 100 200 300 500 1000
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 14. Forward Bias Safe Operating Area
20
18
16
IC/IB1 = 5
14
TJ ≤ 100°C
12
10
8
6
VBE(off) = 1 to 5 V
4
2
VBE(off) = 0 V
0
0
100 200 300 400 500 600 700
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 15. Reverse Bias Safe Operating Area
+15
1 µF
150 Ω 100 Ω
100 µF
MTP8P10
VCE (650 V MAX)
10 µF
MTP8P10
10 mH MUR870
+10
50 Ω
MPF930
MPF930
MUR105
RB1 MUR1100
MUR105
RB2
MTP12N10
T.U.T.
500 µF
MJE210
150 Ω
1 µF
VOff
Note: Test Circuit for Ultra–fast FBSOA
Note: RB2 = 0 and VOff = – 5 Volts
Figure 16. Switching Safe Operating Area
6
Motorola Bipolar Power Transistor Device Data
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