M24256-BFCS6G(2012) 데이터 시트보기 (PDF) - STMicroelectronics
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M24256-BFCS6G Datasheet PDF : 40 Pages
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DC and AC parameters
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Table 16. 400 kHz AC characteristics
Symbol Alt.
Parameter
Min.
Max. Unit
fC
tCHCL
tCLCH
tQL1QL2(1)
tXH1XH2
tXL1XL2
tDXCH
tCLDX
tCLQX(4)
tCLQV(5)
tCHDL
tDLCL
tCHDH
tDHDL
tWLDL(6)(1)
tDHWH(7)(1)
tW
tNS(1)
fSCL
tHIGH
tLOW
tF
tR
tF
tSU:DAT
tHD:DAT
tDH
tAA
tSU:STA
tHD:STA
tSU:STO
tBUF
tSU:WC
tHD:WC
tWR
Clock frequency
Clock pulse width high
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
WC set up time (before the Start condition)
WC hold time (after the Stop condition)
Internal Write cycle duration
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
600
1300
20(2)
(3)
(3)
100
0
100
-
600
600
600
1300
0
1
-
-
400
kHz
-
ns
-
ns
300
ns
(3)
ns
(3)
ns
-
ns
-
ns
-
ns
900
ns
-
ns
-
ns
-
ns
-
ns
-
µs
-
µs
5
ms
80
ns
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
28/40
Doc ID 6757 Rev 30
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