ADSP-2171 데이터 시트보기 (PDF) - Analog Devices

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ADSP-2171

DSP Microcomputer

Analog Devices 

ADSP-2171/ADSP-2172/ADSP-2173

HSR6

0x3FE6

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

2171 HDR5 Write

2171 HDR4 Write

2171 HDR3 Write

2171 HDR2 Write

2171 HDR1 Write

2171 HDR0 Write

Host HDR0 Write

Host HDR1 Write

Host HDR2 Write

Host HDR3 Write

Host HDR4 Write

Host HDR5 Write

HSR7

0x3FE7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000100000000

Overwrite Mode

Software Reset

Control Registers

2171 HDR0 Write

2171 HDR1 Write

2171 HDR2 Write

2171 HDR3 Write

2171 HDR4 Write

2171 HDR5 Write

Biased Rounding

A new mode allows biased rounding in addition to the normal

unbiased rounding. When the BIASRND bit is set to 0, the nor-

mal unbiased rounding operations occur. When the BIASRND

bit is set to 1, biased rounding occurs instead of the normal un-

biased rounding. When operating in biased rounding mode all

rounding operations with MR0 set to 0x8000 will round up,

rather than only rounding odd MR1 values up. For example:

MR value before RND

00-0000-8000

00-0001-8000

00-0000-8001

00-0001-8001

00-0000-7FFF

00-0001-7FFF

biased RND result

00-0001-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

unbiased RND result

00-0000-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

This mode only has an effect when the MR0 register contains

0x8000, all other rounding operation work normally. This mode

was added to allow more efficient implementation of bit speci-

fied algorithms which specify biased rounding such as the GSM

speech compression routines. Unbiased rounding is preferred

for most algorithms.

Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer

Control register.

INSTRUCTION SET DESCRIPTION

The ADSP-217x assembly language instruction set has an alge-

braic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of

the processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

• Every instruction assembles into a single, 24-bit word that can

execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relo-

cated to utilize internal memory and conform to the ADSP-

217x’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an arith-

metic instruction with up to two fetches or one write to pro-

cessor memory space during a single instruction cycle.

Consult the ADSP-2100 Family User’s Manual for a complete

description of the syntax and an instruction set reference.

REV. A

–15–

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