ADSP-2171 데이터 시트보기 (PDF) - Analog Devices

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ADSP-2171

DSP Microcomputer

Analog Devices 

ADSP-2171/ADSP-2172/ADSP-2173

SPORT0 SCLKDIV

Serial Clock Divide Modulus

0x3FF5

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT0 RFSDIV

Receive Frame Sync Divide Modulus

0x3FF4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT0 Autobuffer Control Register

0x3FF3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

00

CLKODIS

CLKOUT Disable Control Bit

BIASRND

MAC Biased Rounding Control Bit

TIREG

Transmit Autobuffer I Register

TMREG

Transmit Autobuffer M Register

RBUF

Receive Autobuffering Enable

TBUF

Transmit Autobuffering Enable

RMREG

Receive Autobuffer M Register

RIREG

Receive Autobuffer I Register

SPORT1 Control Register

0x3FF2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000000000000000

Flag Out (Read Only)

Internal Serial Clock Generation ISCLK

Receive Frame Sync Required RFSR

Receive Frame Sync Width RFSW

Transmit Frame Sync Required TFSR

Transmit Frame Sync Width TFSW

ITFS Internal Transmit Frame Sync Enable

SLEN Serial Word Length

DTYPE Data Format

00 = right justify, zero-fill unused MSBs

01 = right justify, sign extend into unused MSBs

10 = compand using µ-law

11 = compand using A-law

INVRFS Invert Receive Frame Sync

INVTFS Invert Transmit Frame Sync

IRFS Internal Receive Frame Sync Enable

Control Registers

REV. A

–13–

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